1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of fabricating such a device.
2. Description of the Prior Art
LDMOS devices are typically used in high voltage applications, and when designing such LDMOS devices, it is important that the device should have a very high breakdown voltage (Vbd), whilst also exhibiting, when operating, a low on-resistance (Ron). By designing LDMOS devices with low on-resistance and high breakdown voltage, such devices will typically exhibit low power loss in high voltage applications. In addition, by exhibiting a low on-resistance, a high drain current (Idsat) can be achieved when the transistor is in saturation, which increases speed of operation of the device. One problem when designing such LDMOS devices is that techniques and structures that tend to maximise Vbd tend to adversely affect the Ron and vice versa.
In a conventional LDMOS device, a lighter concentration well doping can be provided as an N-minus (NM) region in order to reduce the electric field crowding at the gate edge. However, this lighter concentration well doping tends to increase the Ron. In order to decrease the Ron, it would be necessary to increase the doping concentration of the NM region, but in so doing the breakdown characteristic would be degraded, i.e. Vbd would be reduced.
U.S. Pat. No. 6,448,625 B1 describes a high voltage MOS device in which an N-well region is formed with two areas. As described therein, a first N-well implant process is performed using a first mask. Then, a second N-well implant process is performed using a different mask, with this different mask being offset laterally with respect to the first mask. The second implant process uses a higher concentration implant, and this process results in a well region in which a first area has a high dopant concentration and a second area latterly offset with respect to the first area has a low dopant concentration. The lower dopant concentration in the second area is said to increase the breakdown voltage when the device is blocking voltage, whilst helping to decrease on-resistance when the device is in the “on” state.
U.S. Pat. No. 6,531,355 describes a RESURF LDMOS transistor that includes a RESURF region that is self-aligned to a LOCOS field oxide region. The self-alignment produces a stable breakdown voltage by eliminating degradation associated with geometric misalignment and process tolerance variation. For a given specific-on-resistance, this technique hence produces a RESURF LDMOS device having a stable, predictable breakdown voltage.
U.S. Pat. No. 6,580,131 B2 describes an LDMOS device having two epitaxial N-regions instead of the more traditional single exiptaxial N-region that is used in prior art devices. The lower N-layer has a resistivity that is greater than that of the upper N-layer, which is said to result in an improvement in the trade off between breakdown voltage and on-resistance.
From the above discussion, it will be appreciated that various techniques have been developed with the aim of improving the trade off between breakdown voltage and on-resistance in devices such as LDMOS devices. It would be desirable to provide a technique for manufacturing an LDMOS device which further improves this trade off.